IP Design Challenges
The lifecycle of analog and mixed-signal IP-blocks with frozen GDSII data for use in high-performance systems is at present very short. For the majority of high performance circuits the current performance is a compromise between system requirements and actual process capability.
Processes are being continuously improved and the available process options vary from product to product. Considerable effort is required for designing the analog functions. If a sophisticated macro has been completed in a specific target process, a better performance would be possible in an already available new process. So, for the next product that uses a next generation process, the same type of IP blocks have to be designed once again.
In addition to this, the reuse of a GDSII-fixed IP-block in the same process is limited, since for other applications some conditions may require changes (e.g. die area, power consumption, clock, and timings).
Our Answer – IPGEN® Methodology
A SOC driven design methodology for analog, mixed signal, and also full custom digital circuits has been developed. It covers specification phase, topology selection, design partitioning, optimization and sizing, verification, design style, modeling and design automation. Generic Engineering Model (GEM) enables designers using the handcrafted design style today to significantly boost their efficiency in their own known design environment. The methodology allows to design parameterizable and process retargetable macros for use in SOC. High performance macros can be designed interactively from high abstraction level down to GDSII-level. Real reusability is guaranteed by variable high level parameters allowing to consider a wide set of applications in current and future standard CMOS process generations without need for a time consuming redesign.
The new design style which is based on the Virtual-Grid Symbolic Layout principle defined for digital full custom designs, allows to design with variable design rules. Since the layout is the most complex part in analog circuit design, it focuses on layout generation. The same object oriented design style can be easily adapted for the generation of schematics and symbols. The grid spacing is not only defined by physical design rules but also on special electrical parameters like e.g. cross-talk, matching of components, current density, required driving capability. All these parameters also have influence on the spacing and sizing of the components in an analog design. Therefore, a flexible grid definition with a variable spacing along the x- and y-axisis required. For each grid section a design variable exists. The structured naming scheme which has been defined for the variables containing the technology related data (electrical and physical) guarantees a transparent and concentrated computation of the grid line distances. The end result for the designer is that placement of objectives on the grid can be done without regard to any design rules.
IPGEN Methodology has been developed by experienced design engineers over the course of the past 15 years. Based on this methodology IPGEN launched end of 2006 the 1Stone® Product Family.
The 1Stone® Product Family is a cutting edge, silicon-provendesign automation solution that substantially reduces the development effort for analog and mixed-signal IP's. It also enhances quality and design security significantly.
