Digital Controlled Potentiometer DCP IP

The 1Stone® DCP-IP core is optimized to be used as a DAC and a SAR-ADC in a wide specification range. The architecture is made robust against resistor parameter variations; it takes even advantage of them by applying a statistical averaging approach. Therefore it is able to support resolutions up to 16 bit with guaranteed monotonic and high linearity. Design optimization is enabled by using a behavioral block-level model which can be mapped to individual process profiles and takes various parasitic effects into account. An accurate yield estimation algorithm detects the critical fabrication influence to IP performance in advance. Based on given IP specification and process selection all design views (schematic, layout, and behavioral model and verification test benches) are generated automatically by using executable design descriptions. It is possible to provide a 4 to 16bit configuration in process nodes from 0,6um to 40nm.

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Download DCP IP data sheet